Various techniques have previously been used to manufacture integrated circuits on semiconductor wafers. Optical projection lithography using ultra-violet light is one of the more common techniques. Projection lithography techniques use a mask which is several times larger than the integrated circuit which the process will create. The pattern or circuit is projected from some distance onto a photoresist on a semiconductor wafer.
A step-and-repeat camera system (sometimes referred to as a "stepper") operates by projecting an image containing a portion of an integrated circuit onto one or more chips in a reticle or exposure field on a semiconductor wafer. The stepper then moves to the next exposure site on the wafer and repeats the process. As the line width for integrated circuits on semiconductor devices becomes smaller and smaller, step-and-repeat camera systems with higher aperture numbers or larger lens are used to improve the performance of the lithography process.
As higher number aperture lenses are used to project the integrated circuit onto the wafer, improved resolution is required to meet shrinking line width needs. Increasing the numerical aperture to improve resolution has a negative effect by reducing the depth of focus of the system. At the same time, integrated circuits on semiconductor devices are becoming more complex requiring several more process steps (more topography), which increases the difficulty of maintaining focus across the entire exposure field on a wafer. These requirements increase the demand on the lithography process for greater depth of focus to improve production. Several techniques are being applied to improve depth of focus, such as planarization, the use of smaller wave lengths of light for exposure, and chip leveling on the exposure tools.
A common practice used to compensate for wafer taper and bow, is tilting the wafer before each exposure to match the wafer plane in the exposure field to the step and repeat camera lens plane. This tilting is accomplished by measuring where the surface of the wafer is located, and then tilting the wafer to obtain an optimized plane to lens alignment. Current state-of-the-art steppers often have an alignment system with a fixed beam size which covers a large portion of the exposure field. The beam is reflected from the selected exposure field onto a four-quadrant detector to determine optimum tilting of the wafer. An alternative alignment system used by other steppers is to project multiple (5 to 20) small focus beams which locate at specific distances from each other on the exposure fields. For example, the four corners and the center of a chip might be a typical multiple beam pattern. Based on information from the beam detectors, the wafer is tilted and then exposed.
While prior leveling systems have worked satisfactorily in the past, the patterns for complex integrated circuits are becoming smaller. At the same time, there is increased variation in the size of semiconductor devices which are placed on a wafer. This results in the leveling beam sometimes being larger than the actual exposure field or the multiple beam system projecting onto chips outside the desired exposure field. When a fixed size leveling beam collects data from areas larger than the exposure field, inclination errors may occur between the plane of the exposure field and the plane of the stepper camera lens. This problem is most pronounced around the edge of a wafer. Steppers with multiple leveling beams distributed over the exposure field will have leveling errors if one or more beams fall outside the desired exposure field.
A need has thus arisen for improved leveling of the wafer and the exposure field on the wafer prior to initiating the lithography process.